2009-09-27 23:04:55
The past week has gone to testing the cache some more plus planning the next step. We need some way of bypassing the cache when the videopipeline(s) want to read screen data, since we don't want these reads to fill the cache. That would hurt performance enormously. Henrik will start implementing the ST-RAM snooping, which is one important component of the Videl compatibility. Torbjörn will start implementing the bypass unit mentioned above.
2009-09-20 13:01:30
Some good news regarding the SV. :)
After about 6 weeks Torbjörn finally finished implementing the 32Kbyte cache and CT60-write-FIFO in the FPGA together with the necessary modifications to our internal DDR-controller and CT60-interface.
This weekend we've tested it for real and it seems to work fine. Write accesses are now 100% faster than before and now we've reached 40MB/s (90MHz 060) during SINGLE longword writes (not comparable to the move16 bursts used when measuring the SDRAM performance of the CT60). On our oscilloscope and in simulations we see that the SV gives the 060 a "Transfer Acknowledge (TA)" already during the third cycle after "Transfer Start (TS)", thanks to our write-FIFO, but the 060 itself doesn't start another write until the ninth cycle. So it seems we can't optimize the single accesses any further. To get better performance we need to implement both move16 support and a DMA unit. A small problem with this is that you have to modify the VDI as well so it either uses move16 or the DMA unit (like the CTPCI). Otherwise the VDI will still do single word writes to the screen with sub-optimal speed.
Reads are quite a bit slower (half) than the writes, because we get no advantage from our CT60-write-FIFO, so it's just our 32KB cache that helps us. Unfortunately, accessing the cache from the CT60 still involves quite long latency since the cache is close to the DDR controller and in the DDR clock domain. So the asynchronous bridging eats a lot of cycles etc. MOVE16 support will speed up this greatly though.
2009-09-17 23:31:55
Just a small status report. :) Torbjörn is still busy with implementing the cache inside the SuperVidel FPGA, which will multiply the CT60s bandwidth to the DDR memory several times. This is also necessary in order to develop the ST-RAM snooping, which is a requirement for the Videl compatibility.
