2009-12-15 13:45:17
We have begun adding the Videl registers to our VHDL code of the SuperVidel. The purpose of these registers is to snoop all writes going to the old Videl registers, so that we may interpret what was written and set our SuperVidel registers so that we get the same resolution as the Videl would have produced. That's the main purpose of this entire project. :)
The heavy part of these registers is the interpretation though, not the registers themselves.

We've also been thinking a bit more about the Videl compatibility. During discussions with Peter Persson we realized that the Timer-B of the MFP-chip wouldn't work with our current SuperVidel construction. For this to work we have to feed the video clock of the old Videl into the SuperVidel and let the old Videl work as before. This way you'll get the old Videl picture out through the SuperVidel, as well as the Timer-B HBL-interrupts from the MFP correctly synchronized. In order to feed the old Videl clock into the SuperVidel, a wire will have to be soldered from the old Videl chip. Note that soldering this wire isn't a requirement for getting the SuperVidel to work, but without it the Timer-B won't work correctly in old games and demos. And it's only near the Videl chip that you'll have to solder. The other end of this wire goes to a small 1.27mm connector on the SuperVidel, for easy detachment.

/Henrik

2009-11-25 20:40:51
During the weekend we attended this year's NAS in Falköping, Sweden. It had a very nice atmosphere as always :)

We had set our goal quite low this time: to solder a flat cable at the bottom of the SuperVidel DVI connector to break out the VGA output so we could demonstrate dual screen output via DVI and VGA. The other thing we needed to do was the actual dual screen register settings. It all worked out fine in the end, though we couldn't show any higher than dual 1280x1024x16bit screens, since one of the flat screens we had with us was only 1280x1024. But people got the general concept. :P

For some reason the dual screen output only worked under TOS, but not MiNT/Xaaes. We'll have to investigate this...

/Torbjörn

2009-11-07 10:48:34
We have now successfully added the dual screen functionality. It has been tested at 1680x1050 16bit 60Hz, and seems to work fine. We get both the VGA and DVI signals at the same time, via the DVI-I connector. But since we currently don't have a DVI-I to DVI-D + VGA splitter, we can't actually see both screens at the same time. Time to order a splitter then... :P Henrik has continued researching the Videl register functionality, but no implementation has started yet.

2009-11-02 22:14:33
The ST-RAM snooping, which is a vital part of the Videl compatibility, is now working correctly. :)

Despite our earlier news post that stated the cache was working fine, we've had problems with it in the highest resolutions. But during the last 3-4 weeks we've fixed 6-7 bugs in the VHDL code and now the cache works fine even up to 1680x1050. :)

Currently Torbjörn is adding a second video pipeline to our design, to enable simultaneous dual screen output (VGA+DVI). We don't expect any big problems doing this, since nothing new has to be developed, so we estimate to be able to show you this if you come to NAS (Nordic Atari Show) in Falköping/Sweden on November 20th-22nd. :)

I'm currently investigating how the old Videl registers map to our new registers, in order to implement the most vital part of the Videl compatibility.

2009-10-18 12:43:10
The bypass system is now in place in the FPGA, which means that our video pipeline now works correctly together with the cache. Both the cache and the bypass system took a while to accomplish, because we're always working close to the performance limit of the Spartan3 FPGA (200MHz).

Next thing is to incorporate the ST-RAM snooping that I (Henrik) started.

2009-09-27 23:04:55
The past week has gone to testing the cache some more plus planning the next step. We need some way of bypassing the cache when the videopipeline(s) want to read screen data, since we don't want these reads to fill the cache. That would hurt performance enormously. Henrik will start implementing the ST-RAM snooping, which is one important component of the Videl compatibility. Torbjörn will start implementing the bypass unit mentioned above.