New FW v009 and updated memory map
2016-03-06 19:29:58
Just uploaded a new FW for the SV. :) It has the DDR clock set to the somewhat lower 200MHz (but still up from 185MHz in the older FW versions before rev 7). A new key feature is a FIFO for the SuperBlitter where you can queue up to 56 blitter operations. The odd number comes from that the FIFO has room for 512 longwords, and each blitter operation needs 9 longwords.
Note that you need a JTAG cable to update your SV using these files. This is a security measure, so you can restore your SV if something went wrong. An update program with the v009 FW built in may appear soonish.
The SuperVidelMemoryMap.pdf has also been updated to show this added FIFO in the registers.
New SV firmware v006
2014-01-25 17:08:18
We have just released v006 of the SuperVidel firmware. You find it on our Downloads page. Remember to reload that particular frame or you may not see the page correctly. News in FW v006: Optimimized CT60 clock from 75 to 85MHz. Register bit for triggering Blitter done interrupt.
You may be surprised about the low CT60 clock frequency, but the numbers come from our Xilinx software which is quite conservative. The FPGA itself can handle quite a bit of overclocking.
